Project Title | Domain Name | IEEE Year | DOWNLOAD |
Analysis and Verification of Jitter in Bang Bang Clock and Data Recovery Circuit With a Second Order Loop Filter | VLSI | |
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FSM based High Speed VLSI Architecture for DBUTVF Algorithm | VLSI | |
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Live Demonstration A VLSI Implementation of Time Domain Analog Weighted Sum Calculation Model for Intelligent Processing on Robots | VLSI | |
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A 32 Pixel IDCT Adapted HEVC Intra Prediction VLSI Architecture | VLSI | |
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A Resource Optimized VLSI Architecture for Patient Specific Seizure Detection using Frontal Lobe EEG | VLSI | |
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Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High Level Synthesis | VLSI | |
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Delay Optimization of 4 Bit ALU Designed in FS GDI Technique | VLSI | |
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Implementation of an XOR Based 16 bit Carry Select Adder for Area Delay and Power Minimization | VLSI | |
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An optically reconfigurable gate array workable under a strong gamma radiation environment | VLSI | |
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A low power driver amplifier for Fully Differential ADC | VLSI | |
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Fully Integrated High Voltage Pulse Driver Using Switched Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65 nm CMOS | VLSI | |
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An Untrimmed BJT Based Temperature Sensor with Dynamic Current Gain Compensation in 55 nm CMOS Process | VLSI | |
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A Binary Decision Diagram Approach to On line Testing of Asynchronous Circuits | VLSI | |
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Energy Efficient Power Distribution on Many Core SoC | VLSI | |
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Security Assessment of Microfluidic Fully Programmable Valve Array Biochips | VLSI | |
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A High PSRR Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications | VLSI | |
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VLSI Architectures for 8 Bit Data Comparators for Rank Ordering Image Applications | VLSI | |
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Reactant Minimization for Multi Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models | VLSI | |
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ATPG and Test Compression for Probabilistic Circuits | VLSI | |
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A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms | VLSI | |
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A Novel Test Generation Method for Small Delay Defects with User Defined Fault Model | VLSI | |
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PVT Variations Aware Robust Transistor Sizing for Power Delay Optimal CMOS Digital Circuit Design | VLSI | |
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Optimization of DC DC Power Converter Design with Second Generation HiSIM HV Model | VLSI | |
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Low Latency Semi iterative CORDIC Algorithm using Normalized Angle Recoding and its VLSI Implementation | VLSI | |
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Modeling of Capacitive Coupled Interconnects for Crosstalk Analysis in High Speed VLSI Circuits | VLSI | |
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A Micro Racetrack Optical Resonator Test Structure to Optimize Pattern Approximation in Direct Lithography Technologies | VLSI | |
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VLSI Architectures for Jacobi Symbol Computation | VLSI | |
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System and VLSI Implementation of Phase based View Synthesis | VLSI | |
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Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise | VLSI | |
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Power Efficient Design of Adiabatic Approach for Low Power VLSI Circuits | VLSI | |
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Energy Efficient CNN Inference Accelerator Using Fast Fourier Transform | VLSI | |
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A CMOS 0 85 V 15 8 nW Current and Voltage Reference without Resistors | VLSI | |
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Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA | VLSI | |
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A 50 Gb s Adaptive ADFE with SNR Based Power Management for 2 PAM Systems | VLSI | |
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A 15 bit 20 MS s SHA Less Pipelined ADC Achieving 73 7 dB SNDR with Averaging Correlated Level Shifting Technique | VLSI | |
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A 9mW 6 9GHz 2 5Gb s Proximity Transmitter with Combined OOK BPSK Modulation for Low Power Mobile Connectivity | VLSI | |
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A High Performance Low Energy Compact Masked 128 Bit AES in 22nm CMOS Technology | VLSI | |
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EcoSim A Smartphone Based Sensor Node Emulator with Native Sensors and Protocol Stack | VLSI | |
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High Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks | VLSI | |
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BlueBox A Complete Recorder for Code Blue Events in Hospitals | VLSI | |
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An Analog Front End Circuit for CO2 Sensor Readout in 0 18 m CMOS Process | VLSI | |
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High Throughput 64K point FFT Processor for THz Imaging Radar System | VLSI | |
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A Light Energy Harvesting Single Inductor Dual Input Dual Output Converter for WSN | VLSI | |
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Heterogeneous Computing for Edge AI | VLSI | |
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User Friendly Compact Model of Magnetic Tunnel Junctions for Circuit Simulation Based on Switching Probability | VLSI | |
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Supervised Learning Congestion Predictor For Routability Driven Global Routing | VLSI | |
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Design and Analysis of Data Pattern Insensitive Phase Tracking Receivers with Fully Balanced FSK Modulation | VLSI | |
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A 30 ns 16 Mb 2 b cell Embedded Flash with Ramped Gate Time Domain Sensing Scheme for Automotive Application | VLSI | |
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Efficient Write Scheme for Algorithm Based Multi Ported Memory | VLSI | |
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Primitive Concept Identification In A Given Set Of Wafer Maps | VLSI | |
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10 Bit SAR ADC With Novel Pseudo Random Capacitor Switching Scheme | VLSI | |
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A perspective on NVRAM technology for future computing system | VLSI | |
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A Reliable Low Cost Low Energy Physically Unclonable Function Circuit Through Effective Filtering | VLSI | |
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A Lightweight 1 16 pJ bit Processor for the Authenticated Encryption Scheme KetjeSR | VLSI | |
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Reversible Scan Based Diagnostic Patterns | VLSI | |
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Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks | VLSI | |
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A 39 GHz Reflection Type Phase Shifter for Reflectarray Antenna Application | VLSI | |
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Efficient Dynamic Fixed Point Quantization of CNN Inference Accelerators for Edge Devices | VLSI | |
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Machine Learning Applications and Opportunities in IC Design Flow | VLSI | |
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NNSim A Fast and Accurate SystemC TLM Simulator for Deep Convolutional Neural Network Accelerators | VLSI | |
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Micro Architecture Optimization for Low Power Bitcoin Mining ASICs | VLSI | |
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Event Driven Model for High Speed End to End Simulations of Transmission System with Non Linear Optical Elements and Cascaded Clock and Data Recovery Circuits | VLSI | |
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A Current Mode Differential Sensing CMOS Imager for Optical Linear Encoder | VLSI | |
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TEMPO Thermal Efficient Management of Power in High Throughput Network Switches | VLSI | |
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A Variation Tolerant Bitline Leakage Sensing Scheme for Near Threshold SRAMs | VLSI | |
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Customization of a Deep Learning Accelerator | VLSI | |
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A Power Efficient Bi Directional Readout Interface Circuit for Cyclic Voltammetry Electrochemical Sensors | VLSI | |
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Process Design Kit and Design Automation for Flexible Hybrid Electronics | VLSI | |
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ONNC Based Software Development Platform for Configurable NVDLA Designs | VLSI | |
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Design of A Bit Serial Artificial Neuron VLSI Architecture with Early Termination | VLSI | |
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Clocking for HPC Design Challenges and Experience Sharing | VLSI | |
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High Throughput and High Speed Polar Decoder VLSI Architecture for 5G New Radio | VLSI | |
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Silicon Process Impact on 5G NR mmWave Front End Design and Performance | VLSI | |
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Beyond Digital Neuromorphic Hardware Time Based and Flash Based Designs | VLSI | |
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Ultraflexible Amplification Circuits for Imperceptible Brain Monitoring System | VLSI | |
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Scalable AI Computing Lifecycle | VLSI | |
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Silicon Technologies for Next Generation 5G Architectures and Applications | VLSI | |
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Progress in Neuromorphic Computing Drawing Inspiration from Nature for Gains in AI and Computing | VLSI | |
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Research Status of Silicon Photonic Integration in Taiwan s Academia | VLSI | |
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