Project Title | Domain Name | IEEE Year | DOWNLOAD |
Improving Error Correction Codes for Multiplier Cel Upsets in Space Applications | VLSI | 2018 |
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A Simple Yet Efficient Accuracy Configurable Adder Design | VLSI | 2018 |
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Feedback Based Low Power Soft Error Tolerant Design for Dual Modular Redundancy | VLSI | 2018 |
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A Fast Locking Low Jitter Pulsewidth Control Loop for High Speed ADC | VLSI | 2018 |
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Fast Neural Network Training on FPGA Using Quasi Newton Optimization Method | VLSI | 2018 |
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Multilevel Half Rate Phase Detector for Clock and Data Recovery Circuits | VLSI | 2018 |
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Algorithm and VLSI Architecture Design of Proportionate Type LMS Adaptive Filters for Sparse System Identification | VLSI | 2018 |
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Low Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption | VLSI | 2018 |
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SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability | VLSI | 2018 |
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A 3 2 GHz Supply Noise Insensitive PLL Using a Gate Voltage Boosted Source Follower Regulator and Residual Noise Cancellation | VLSI | 2018 |
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Combating Data Leakage Trojans in Commercial and ASIC Applications With Time Division Multiplexing and Random Encoding | VLSI | 2018 |
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A 12 bit 40 MS s SAR ADC With a Fast Binary Window DAC Switching Scheme | VLSI | 2018 |
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A Variable Size FFT Hardware Accelerator Based on Matrix Transposition | VLSI | 2018 |
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A 0 9 V 12 bit 100 MS s 14 6 fJ Conversion Step SAR ADC in 40 nm CMOS | VLSI | 2018 |
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Low Power and Fast Full Adder by Exploring New XOR andX NOR Gates | VLSI | 2018 |
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A Flexible Wildcard Pattern Matching Accelerator via Simultaneous Discrete Finite Automata | VLSI | 2018 |
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Securing the PRESENT Block Cipher Against Combined Side Channel Analysis and Fault Attacks | VLSI | 2018 |
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Low Complexity Methodology for Complex Square Root Computation | VLSI | 2018 |
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ULV Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures | VLSI | 2018 |
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Vector Processing Aware Advanced Clock Gating Techniques for Low Power Fused Multiply Add | VLSI | 2018 |
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A High Accuracy Programmable Pulse Generator With a 10 ps Timing Resolution | VLSI | 2018 |
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Low Phase Noise Ku Band VCO With Optimal Switched Capacitor Bank Design | VLSI | 2018 |
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Analysis and Design of Cost Effective High Throughput LDPC Decoders | VLSI | 2018 |
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Basic Set Trellis Min Max Decoder Architecture for Nonbinary LDPC Codes With High Order Galois Fields | VLSI | 2018 |
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Approximate Hybrid High Radix Encoding for Energy Efficient Inexact Multipliers | VLSI | 2018 |
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A 588 Gb s LDPC Decoder Based on Finite Alphabet Message Passing | VLSI | 2018 |
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The Implementation of the Improved OMP for AIC Reconstruction Based on Parallel Index Selection | VLSI | 2018 |
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Design and FPGA Implementation of a Reconfigurable Digital Down Converter for Wideband Applications | VLSI | 2018 |
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VLSI Design of an ML Based Power Efficient Motion Estimation Controller for Intelligent Mobile Systems | VLSI | 2018 |
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Extending 3 bit Burst Error Correction Codes With Quadruple Adjacent Error Correction | VLSI | 2018 |
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An Energy Efficient Programmable Manycore Accelerator for Personalized Biomedical Applications | VLSI | 2018 |
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Approximate Sum of Products Designs Based on Distributed Arithmetic | VLSI | 2018 |
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An Efficient Fault Tolerance Design for Integer Parallel Matrix Vector Multiplications | VLSI | 2018 |
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A Reconfigurable LDPC Decoder Optimized for 802 11n ac Applications | VLSI | 2018 |
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A Fast and Low Complexity Operator for the Computation of the Arctangent of a Complex Number | VLSI | 2018 |
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Design of an Area Efficient Million Bit Integer Multiplier Using Double Modulus NTT | VLSI | 2018 |
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Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities | VLSI | 2018 |
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Efficient FPGA Mapping of Pipeline SDF FFT Cores | VLSI | 2018 |
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A 0 65 V 500 MHz Integrated Dynamic and Static RAM for Error Tolerant Applications | VLSI | 2018 |
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Design of Temperature Aware Low Voltage 8T SRAM in SOI Technology for High Temperature Operation 25 C 300 C | VLSI | 2018 |
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Approximate Error Detection With Stochastic Checkers | VLSI | 2018 |
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A Residue to Binary Converter for the Extended Four Moduli Set 2n 1 2n 1 22n 1 22n p | VLSI | 2018 |
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A Closed Form Expression for Minimum Operating Voltage of CMOS D Flip Flop | VLSI | 2018 |
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A 128 Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications | VLSI | 2018 |
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A 0 45 V 147 375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures | VLSI | 2017 |
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A 92 dB DR 24 3 mW 1 25 MHz BW Sigma Delta Modulator Using Dynamically Biased Op Amp Sharing | VLSI | 2017 |
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Energy Efficient TCAM Search Engine Design Using Priority Decision in Memory Technology | VLSI | 2017 |
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On Micro architectural Mechanisms for Cache Wear out Reduction | VLSI | 2017 |
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Sense Amplifier Half Buffer SAHB A Low Power High Performance Asynchronous Logic QDI Cell Template | VLSI | 2017 |
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A 100 mA 99 11 Current Efficiency 2 mVppRipple Digitally Controlled LDO with Active Ripple Suppression | VLSI | 2017 |
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Preweighted Linearized VCO Analog to Digital Converter | VLSI | 2017 |
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A Fault Tolerance Technique for Combinational Circuits Based on Selective Transistor Redundancy | VLSI | 2017 |
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A 65 nm CMOS Constant Current Source with Reduced PVT Variation | VLSI | 2017 |
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An All MOSFET Sub 1 V Voltage Reference With a 51 dB PSR up to 60 MHz | VLSI | 2017 |
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Conditional Boosting Flip Flop for Near Threshold Voltage Application | VLSI | 2017 |
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A 0 1 2 GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130 nm CMOS | VLSI | 2017 |
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A High Speed and Power Efficient Voltage Level Shifter for Dual Supply Applications | VLSI | 2017 |
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Probability Driven Multi bit Flip Flop Integration With Clock Gating | VLSI | 2017 |
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Area and Energy Efficient Complementary Dual Modular Redundancy Dynamic Memory for Space Applications | VLSI | 2017 |
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Delay Analysis for Current Mode Threshold Logic Gate Designs | VLSI | 2017 |
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Title 10T SRAM Using Half VDD Precharge and Row Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage | VLSI | 2017 |
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Analysis and Design of a Low Voltage Low Power Double Tail Comparator | VLSI | 2017 |
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Low Power Design for a Digit Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique | VLSI | 2017 |
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Temporarily Fine Grained Sleep Technique for Near and Sub threshold Parallel Architectures | VLSI | 2017 |
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Multicast Aware High Performance Wireless Network on Chip Architectures | VLSI | 2017 |
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Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction | VLSI | 2017 |
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COMEDI Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits | VLSI | 2017 |
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Design of Power and Area Efficient Approximate Multipliers | VLSI | 2017 |
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Time Encoded Values for Highly Efficient Stochastic Circuits | VLSI | 2017 |
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Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations | VLSI | 2017 |
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An FPGA Based Hardware Accelerator for Traffic Sign Detection | VLSI | 2017 |
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Dual Quality 4 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers | VLSI | 2017 |
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Energy Efficient Reduce and Rank Using Input Adaptive Approximations | VLSI | 2017 |
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RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal Processing | VLSI | 2017 |
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A Dual Clock VLSI Design of H 265 Sample Adaptive Offset Estimation for 8k Ultra HD TV Encoding | VLSI | 2017 |
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Energy Efficient VLSI Realization of Binary64 Division with Redundant Number Systems | VLSI | 2017 |
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Antiwear Leveling Design for SSDs With Hybrid ECC Capability | VLSI | 2017 |
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Low Complexity Transformed Encoder Architectures for Quasi Cyclic Non binary LDPC Codes Over Subfields | VLSI | 2017 |
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FPGA Realization of Low Register Systolic All One Polynomial Multipliers over GF 2m and Their Applications in Trinomial Multipliers | VLSI | 2017 |
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Sign Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication | VLSI | 2017 |
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Hybrid LUT Multiplexer FPGA Logic Architectures | VLSI | 2017 |
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Low Complexity Digit Serial Multiplier Over GF 2m Based on Efficient Toeplitz Block Toeplitz Matrix Vector Product Decomposition | VLSI | 2017 |
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Efficient Soft Cancelation Decoder Architectures for Polar Codes | VLSI | 2017 |
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Hybrid Hardware Software Floating Point Implementations for Optimized Area and Throughput Tradeoffs | VLSI | 2017 |
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ENFIRE A Spatio Temporal Fine Grained Reconfigurable Hardware | VLSI | 2017 |
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A Method to Design Single Error Correction Codes with Fast Decoding for a Subset of Critical Bits | VLSI | 2017 |
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VLSI Design of 64bit 64bit High Performance Multiplier with Redundant Binary Encoding | VLSI | 2017 |
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Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares | VLSI | 2017 |
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A High Efficiency 6 78 MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission | VLSI | 2017 |
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Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm | VLSI | 2017 |
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Hardware Efficient Built In Redundancy Analysis for Memory With Various Spares | VLSI | 2017 |
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A 2 4 3 6 GHz Wideband Sub harmonically Injection Locked PLL with Adaptive Injection Timing Alignment Technique | VLSI | 2017 |
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An On Chip Monitoring Circuit for Signal Integrity Analysis of 8 Gb s Chip to Chip Interfaces With Source Synchronous Clock | VLSI | 2017 |
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High Speed and Low Latency ECC Processor Implementation Over GF 2m on FPGA | VLSI | 2017 |
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Efficient Designs of Multi ported Memory on FPGA | VLSI | 2017 |
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Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map | VLSI | 2017 |
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Scalable Approach for Power Droop Reduction During Scan Based Logic BIST | VLSI | 2017 |
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High Speed Parallel LFSR Architectures Based on Improved State Space Transformations | VLSI | 2017 |
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High Throughput and Energy Efficient Belief Propagation Polar Code Decoder | VLSI | 2017 |
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Fault Diagnosis Schemes for Low Energy Block Cipher Midori Benchmarked on FPGA | VLSI | 2017 |
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Write Amount Aware Management Policies for STT RAM Caches | VLSI | 2017 |
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Resource Efficient SRAM based Ternary Content Addressable Memory | VLSI | 2017 |
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A Way Filtering Based Dynamic Logical Associative Cache Architecture for Low Energy Consumption | VLSI | 2017 |
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Low Power Scan Based Built In Self Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding | VLSI | 2017 |
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Coordinate Rotation Based Low Complexity K Means Clustering Architecture | VLSI | 2017 |
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Adaptive Multi bit Crosstalk Aware Error Control Coding Scheme for On Chip Communication | VLSI | 2017 |
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A 2 5 ps Bin Size and 6 7 ps Resolution FPGA Time to Digital Converter Based on Delay Wrapping and Averaging | VLSI | 2017 |
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Analysis and Verification of Jitter in Bang Bang Clock and Data Recovery Circuit With a Second Order Loop Filter | VLSI | |
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FSM based High Speed VLSI Architecture for DBUTVF Algorithm | VLSI | |
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Live Demonstration A VLSI Implementation of Time Domain Analog Weighted Sum Calculation Model for Intelligent Processing on Robots | VLSI | |
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A 32 Pixel IDCT Adapted HEVC Intra Prediction VLSI Architecture | VLSI | |
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A Resource Optimized VLSI Architecture for Patient Specific Seizure Detection using Frontal Lobe EEG | VLSI | |
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Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High Level Synthesis | VLSI | |
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Delay Optimization of 4 Bit ALU Designed in FS GDI Technique | VLSI | |
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Implementation of an XOR Based 16 bit Carry Select Adder for Area Delay and Power Minimization | VLSI | |
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An optically reconfigurable gate array workable under a strong gamma radiation environment | VLSI | |
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A low power driver amplifier for Fully Differential ADC | VLSI | |
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Fully Integrated High Voltage Pulse Driver Using Switched Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65 nm CMOS | VLSI | |
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An Untrimmed BJT Based Temperature Sensor with Dynamic Current Gain Compensation in 55 nm CMOS Process | VLSI | |
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A Binary Decision Diagram Approach to On line Testing of Asynchronous Circuits | VLSI | |
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Energy Efficient Power Distribution on Many Core SoC | VLSI | |
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Security Assessment of Microfluidic Fully Programmable Valve Array Biochips | VLSI | |
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A High PSRR Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications | VLSI | |
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VLSI Architectures for 8 Bit Data Comparators for Rank Ordering Image Applications | VLSI | |
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Reactant Minimization for Multi Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models | VLSI | |
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ATPG and Test Compression for Probabilistic Circuits | VLSI | |
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A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms | VLSI | |
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A Novel Test Generation Method for Small Delay Defects with User Defined Fault Model | VLSI | |
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PVT Variations Aware Robust Transistor Sizing for Power Delay Optimal CMOS Digital Circuit Design | VLSI | |
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Optimization of DC DC Power Converter Design with Second Generation HiSIM HV Model | VLSI | |
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Low Latency Semi iterative CORDIC Algorithm using Normalized Angle Recoding and its VLSI Implementation | VLSI | |
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Modeling of Capacitive Coupled Interconnects for Crosstalk Analysis in High Speed VLSI Circuits | VLSI | |
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A Micro Racetrack Optical Resonator Test Structure to Optimize Pattern Approximation in Direct Lithography Technologies | VLSI | |
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VLSI Architectures for Jacobi Symbol Computation | VLSI | |
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System and VLSI Implementation of Phase based View Synthesis | VLSI | |
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Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise | VLSI | |
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Power Efficient Design of Adiabatic Approach for Low Power VLSI Circuits | VLSI | |
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Energy Efficient CNN Inference Accelerator Using Fast Fourier Transform | VLSI | |
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A CMOS 0 85 V 15 8 nW Current and Voltage Reference without Resistors | VLSI | |
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Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA | VLSI | |
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A 50 Gb s Adaptive ADFE with SNR Based Power Management for 2 PAM Systems | VLSI | |
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A 15 bit 20 MS s SHA Less Pipelined ADC Achieving 73 7 dB SNDR with Averaging Correlated Level Shifting Technique | VLSI | |
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A 9mW 6 9GHz 2 5Gb s Proximity Transmitter with Combined OOK BPSK Modulation for Low Power Mobile Connectivity | VLSI | |
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A High Performance Low Energy Compact Masked 128 Bit AES in 22nm CMOS Technology | VLSI | |
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EcoSim A Smartphone Based Sensor Node Emulator with Native Sensors and Protocol Stack | VLSI | |
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High Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks | VLSI | |
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BlueBox A Complete Recorder for Code Blue Events in Hospitals | VLSI | |
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An Analog Front End Circuit for CO2 Sensor Readout in 0 18 m CMOS Process | VLSI | |
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High Throughput 64K point FFT Processor for THz Imaging Radar System | VLSI | |
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A Light Energy Harvesting Single Inductor Dual Input Dual Output Converter for WSN | VLSI | |
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Heterogeneous Computing for Edge AI | VLSI | |
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User Friendly Compact Model of Magnetic Tunnel Junctions for Circuit Simulation Based on Switching Probability | VLSI | |
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Supervised Learning Congestion Predictor For Routability Driven Global Routing | VLSI | |
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Design and Analysis of Data Pattern Insensitive Phase Tracking Receivers with Fully Balanced FSK Modulation | VLSI | |
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A 30 ns 16 Mb 2 b cell Embedded Flash with Ramped Gate Time Domain Sensing Scheme for Automotive Application | VLSI | |
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Efficient Write Scheme for Algorithm Based Multi Ported Memory | VLSI | |
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Primitive Concept Identification In A Given Set Of Wafer Maps | VLSI | |
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10 Bit SAR ADC With Novel Pseudo Random Capacitor Switching Scheme | VLSI | |
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A perspective on NVRAM technology for future computing system | VLSI | |
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A Reliable Low Cost Low Energy Physically Unclonable Function Circuit Through Effective Filtering | VLSI | |
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A Lightweight 1 16 pJ bit Processor for the Authenticated Encryption Scheme KetjeSR | VLSI | |
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Reversible Scan Based Diagnostic Patterns | VLSI | |
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Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks | VLSI | |
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A 39 GHz Reflection Type Phase Shifter for Reflectarray Antenna Application | VLSI | |
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Efficient Dynamic Fixed Point Quantization of CNN Inference Accelerators for Edge Devices | VLSI | |
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Machine Learning Applications and Opportunities in IC Design Flow | VLSI | |
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NNSim A Fast and Accurate SystemC TLM Simulator for Deep Convolutional Neural Network Accelerators | VLSI | |
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Micro Architecture Optimization for Low Power Bitcoin Mining ASICs | VLSI | |
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Event Driven Model for High Speed End to End Simulations of Transmission System with Non Linear Optical Elements and Cascaded Clock and Data Recovery Circuits | VLSI | |
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A Current Mode Differential Sensing CMOS Imager for Optical Linear Encoder | VLSI | |
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TEMPO Thermal Efficient Management of Power in High Throughput Network Switches | VLSI | |
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A Variation Tolerant Bitline Leakage Sensing Scheme for Near Threshold SRAMs | VLSI | |
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Customization of a Deep Learning Accelerator | VLSI | |
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A Power Efficient Bi Directional Readout Interface Circuit for Cyclic Voltammetry Electrochemical Sensors | VLSI | |
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Process Design Kit and Design Automation for Flexible Hybrid Electronics | VLSI | |
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ONNC Based Software Development Platform for Configurable NVDLA Designs | VLSI | |
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Design of A Bit Serial Artificial Neuron VLSI Architecture with Early Termination | VLSI | |
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Clocking for HPC Design Challenges and Experience Sharing | VLSI | |
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High Throughput and High Speed Polar Decoder VLSI Architecture for 5G New Radio | VLSI | |
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Silicon Process Impact on 5G NR mmWave Front End Design and Performance | VLSI | |
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Beyond Digital Neuromorphic Hardware Time Based and Flash Based Designs | VLSI | |
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Ultraflexible Amplification Circuits for Imperceptible Brain Monitoring System | VLSI | |
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Scalable AI Computing Lifecycle | VLSI | |
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Silicon Technologies for Next Generation 5G Architectures and Applications | VLSI | |
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Progress in Neuromorphic Computing Drawing Inspiration from Nature for Gains in AI and Computing | VLSI | |
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Research Status of Silicon Photonic Integration in Taiwan s Academia | VLSI | |
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Failure Root Cause Analysis Automation on Functional Simulation Regressions | VLSI | 2018-2019 |
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CRISP Center for Research on Intelligent Storage and Processing in Memory | VLSI | 2018-2019 |
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R D Activities for 5G Radio Access Technologies Using SHF Bands and Co Creation of New Services Using 5G | VLSI | 2018-2019 |
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TSRI Silicon Photonics Design Platform Standardization and Collaboration | VLSI | 2018-2019 |
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New Memory Technology Design and Architecture Co Optimization to Enable Future System Needs | VLSI | 2018-2019 |
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Flexible Circuits and Systems for Smart Biomedical Applications | VLSI | 2018-2019 |
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Future of Computing and Sensing Systems for Embedded Applications | VLSI | 2018-2019 |
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Embedded Memories for Silicon In Package Optimization of Memory Subsystem from IoT to Machine Learning | VLSI | 2018-2019 |
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VLSI Architectures for ORVD Trellis based MIMO Detection | VLSI | 2018-2019 |
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Embedded Memory The Future of Emerging Memories | VLSI | 2018-2019 |
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Journey to 5G | VLSI | 2018-2019 |
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Study on Early Capture Based VLSI Aging Monitoring Techniques | VLSI | 2018-2019 |
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Evolution and Advances of the Nonvolatile Memories and Applications | VLSI | 2018-2019 |
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Development and Evaluation of Low SHF Band C RAN Massive MIMO System for 5G | VLSI | 2018-2019 |
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EUVL Optics Status and Future Perspectives | VLSI | 2018-2019 |
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Using a Complete Flow for Photonic Integrated Circuits to Improve Product Development Time | VLSI | 2018-2019 |
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R D Activities for Capacity Enhancement Using 5G Ultra High Density Distributed Antenna Systems | VLSI | 2018-2019 |
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Semiconductor for 5G | VLSI | 2018-2019 |
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Autonomous Driving Technologies and Computing Platform | VLSI | 2018-2019 |
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Slow Down in Power Scaling and the End of Moore s Law | VLSI | 2018-2019 |
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