Project Title Domain Name IEEE Year DOWNLOAD A 0 45 V 147 375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures VLSI 2017 Download A 92 dB DR 24 3 mW 1 25 MHz BW Sigma Delta Modulator Using Dynamically Biased Op Amp Sharing VLSI 2017 Download Energy Efficient TCAM Search Engine Design Using Priority Decision in Memory Technology VLSI 2017 Download On Micro architectural Mechanisms for Cache Wear out Reduction VLSI 2017 Download Sense Amplifier Half Buffer SAHB A Low Power High Performance Asynchronous Logic QDI Cell Template VLSI 2017 Download A 100 mA 99 11 Current Efficiency 2 mVppRipple Digitally Controlled LDO with Active Ripple Suppression VLSI 2017 Download Preweighted Linearized VCO Analog to Digital Converter VLSI 2017 Download A Fault Tolerance Technique for Combinational Circuits Based on Selective Transistor Redundancy VLSI 2017 Download A 65 nm CMOS Constant Current Source with Reduced PVT Variation VLSI 2017 Download An All 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Toeplitz Matrix Vector Product Decomposition VLSI 2017 Download Efficient Soft Cancelation Decoder Architectures for Polar Codes VLSI 2017 Download Hybrid Hardware Software Floating Point Implementations for Optimized Area and Throughput Tradeoffs VLSI 2017 Download ENFIRE A Spatio Temporal Fine Grained Reconfigurable Hardware VLSI 2017 Download A Method to Design Single Error Correction Codes with Fast Decoding for a Subset of Critical Bits VLSI 2017 Download VLSI Design of 64bit 64bit High Performance Multiplier with Redundant Binary Encoding VLSI 2017 Download Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares VLSI 2017 Download A High Efficiency 6 78 MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission VLSI 2017 Download Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm VLSI 2017 Download Hardware Efficient Built In Redundancy Analysis for Memory With Various Spares VLSI 2017 Download A 2 4 3 6 GHz Wideband Sub harmonically Injection Locked PLL with Adaptive Injection Timing Alignment Technique VLSI 2017 Download An On Chip Monitoring Circuit for Signal Integrity Analysis of 8 Gb s Chip to Chip Interfaces With Source Synchronous Clock VLSI 2017 Download High Speed and Low Latency ECC Processor Implementation Over GF 2m on FPGA VLSI 2017 Download Efficient Designs of Multi ported Memory on FPGA VLSI 2017 Download Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map VLSI 2017 Download Scalable Approach for Power Droop Reduction During Scan Based Logic BIST VLSI 2017 Download High Speed Parallel LFSR Architectures Based on Improved State Space Transformations VLSI 2017 Download High Throughput and Energy Efficient Belief Propagation Polar Code Decoder VLSI 2017 Download Fault Diagnosis Schemes for Low Energy Block Cipher Midori Benchmarked on FPGA VLSI 2017 Download Write Amount Aware Management Policies for STT RAM Caches VLSI 2017 Download Resource Efficient SRAM based Ternary Content Addressable Memory VLSI 2017 Download A Way Filtering Based Dynamic Logical Associative Cache Architecture for Low Energy Consumption VLSI 2017 Download Low Power Scan Based Built In Self Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding VLSI 2017 Download Coordinate Rotation Based Low Complexity K Means Clustering Architecture VLSI 2017 Download Adaptive Multi bit Crosstalk Aware Error Control Coding Scheme for On Chip Communication VLSI 2017 Download A 2 5 ps Bin Size and 6 7 ps Resolution FPGA Time to Digital Converter Based on Delay Wrapping and Averaging VLSI 2017 Download