Project TitleDomain NameIEEE YearDOWNLOAD
A 0 45 V 147 375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation ArchitecturesVLSI2017 Download
A 92 dB DR 24 3 mW 1 25 MHz BW Sigma Delta Modulator Using Dynamically Biased Op Amp SharingVLSI2017 Download
Energy Efficient TCAM Search Engine Design Using Priority Decision in Memory TechnologyVLSI2017 Download
On Micro architectural Mechanisms for Cache Wear out ReductionVLSI2017 Download
Sense Amplifier Half Buffer SAHB A Low Power High Performance Asynchronous Logic QDI Cell TemplateVLSI2017 Download
A 100 mA 99 11 Current Efficiency 2 mVppRipple Digitally Controlled LDO with Active Ripple SuppressionVLSI2017 Download
Preweighted Linearized VCO Analog to Digital ConverterVLSI2017 Download
A Fault Tolerance Technique for Combinational Circuits Based on Selective Transistor RedundancyVLSI2017 Download
A 65 nm CMOS Constant Current Source with Reduced PVT VariationVLSI2017 Download
An All MOSFET Sub 1 V Voltage Reference With a 51 dB PSR up to 60 MHzVLSI2017 Download
Conditional Boosting Flip Flop for Near Threshold Voltage ApplicationVLSI2017 Download
A 0 1 2 GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130 nm CMOSVLSI2017 Download
A High Speed and Power Efficient Voltage Level Shifter for Dual Supply ApplicationsVLSI2017 Download
Probability Driven Multi bit Flip Flop Integration With Clock GatingVLSI2017 Download
Area and Energy Efficient Complementary Dual Modular Redundancy Dynamic Memory for Space ApplicationsVLSI2017 Download
Delay Analysis for Current Mode Threshold Logic Gate DesignsVLSI2017 Download
Title 10T SRAM Using Half VDD Precharge and Row Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage VLSI2017 Download
Analysis and Design of a Low Voltage Low Power Double Tail ComparatorVLSI2017 Download
Low Power Design for a Digit Serial Polynomial Basis Finite Field Multiplier Using Factoring TechniqueVLSI2017 Download
Temporarily Fine Grained Sleep Technique for Near and Sub threshold Parallel ArchitecturesVLSI2017 Download
Multicast Aware High Performance Wireless Network on Chip ArchitecturesVLSI2017 Download
Reordering Tests for Efficient Fail Data Collection and Tester Time ReductionVLSI2017 Download
COMEDI Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic CircuitsVLSI2017 Download
Design of Power and Area Efficient Approximate MultipliersVLSI2017 Download
Time Encoded Values for Highly Efficient Stochastic CircuitsVLSI2017 Download
Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations VLSI2017 Download
An FPGA Based Hardware Accelerator for Traffic Sign Detection VLSI2017 Download
Dual Quality 4 2 Compressors for Utilizing in Dynamic Accuracy Configurable MultipliersVLSI2017 Download
Energy Efficient Reduce and Rank Using Input Adaptive ApproximationsVLSI2017 Download
RoBA Multiplier A Rounding Based Approximate Multiplier for High Speed yet Energy Efficient Digital Signal ProcessingVLSI2017 Download
A Dual Clock VLSI Design of H 265 Sample Adaptive Offset Estimation for 8k Ultra HD TV EncodingVLSI2017 Download
Energy Efficient VLSI Realization of Binary64 Division with Redundant Number SystemsVLSI2017 Download
Antiwear Leveling Design for SSDs With Hybrid ECC CapabilityVLSI2017 Download
Low Complexity Transformed Encoder Architectures for Quasi Cyclic Non binary LDPC Codes Over SubfieldsVLSI2017 Download
FPGA Realization of Low Register Systolic All One Polynomial Multipliers over GF 2m and Their Applications in Trinomial MultipliersVLSI2017 Download
Sign Magnitude Encoding for Efficient VLSI Realization of Decimal MultiplicationVLSI2017 Download
Hybrid LUT Multiplexer FPGA Logic ArchitecturesVLSI2017 Download
Low Complexity Digit Serial Multiplier Over GF 2m Based on Efficient Toeplitz Block Toeplitz Matrix Vector Product DecompositionVLSI2017 Download
Efficient Soft Cancelation Decoder Architectures for Polar CodesVLSI2017 Download
Hybrid Hardware Software Floating Point Implementations for Optimized Area and Throughput TradeoffsVLSI2017 Download
ENFIRE A Spatio Temporal Fine Grained Reconfigurable HardwareVLSI2017 Download
A Method to Design Single Error Correction Codes with Fast Decoding for a Subset of Critical BitsVLSI2017 Download
VLSI Design of 64bit 64bit High Performance Multiplier with Redundant Binary EncodingVLSI2017 Download
Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered ComparesVLSI2017 Download
A High Efficiency 6 78 MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power TransmissionVLSI2017 Download
Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search AlgorithmVLSI2017 Download
Hardware Efficient Built In Redundancy Analysis for Memory With Various SparesVLSI2017 Download
A 2 4 3 6 GHz Wideband Sub harmonically Injection Locked PLL with Adaptive Injection Timing Alignment TechniqueVLSI2017 Download
An On Chip Monitoring Circuit for Signal Integrity Analysis of 8 Gb s Chip to Chip Interfaces With Source Synchronous ClockVLSI2017 Download
High Speed and Low Latency ECC Processor Implementation Over GF 2m on FPGAVLSI2017 Download
Efficient Designs of Multi ported Memory on FPGAVLSI2017 Download
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map VLSI2017 Download
Scalable Approach for Power Droop Reduction During Scan Based Logic BIST VLSI2017 Download
High Speed Parallel LFSR Architectures Based on Improved State Space Transformations VLSI2017 Download
High Throughput and Energy Efficient Belief Propagation Polar Code DecoderVLSI2017 Download
Fault Diagnosis Schemes for Low Energy Block Cipher Midori Benchmarked on FPGAVLSI2017 Download
Write Amount Aware Management Policies for STT RAM CachesVLSI2017 Download
Resource Efficient SRAM based Ternary Content Addressable MemoryVLSI2017 Download
A Way Filtering Based Dynamic Logical Associative Cache Architecture for Low Energy ConsumptionVLSI2017 Download
Low Power Scan Based Built In Self Test Based on Weighted Pseudorandom Test Pattern Generation and ReseedingVLSI2017 Download
Coordinate Rotation Based Low Complexity K Means Clustering ArchitectureVLSI2017 Download
Adaptive Multi bit Crosstalk Aware Error Control Coding Scheme for On Chip CommunicationVLSI2017 Download
A 2 5 ps Bin Size and 6 7 ps Resolution FPGA Time to Digital Converter Based on Delay Wrapping and AveragingVLSI2017 Download

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