Project Title Domain Name IEEE Year DOWNLOAD Improving Error Correction Codes for Multiplier Cel Upsets in Space Applications VLSI 2018 Download A Simple Yet Efficient Accuracy Configurable Adder Design VLSI 2018 Download Feedback Based Low Power Soft Error Tolerant Design for Dual Modular Redundancy VLSI 2018 Download A Fast Locking Low Jitter Pulsewidth Control Loop for High Speed ADC VLSI 2018 Download Fast Neural Network Training on FPGA Using Quasi Newton Optimization Method VLSI 2018 Download Multilevel Half Rate Phase Detector for Clock and Data Recovery Circuits VLSI 2018 Download Algorithm and VLSI Architecture Design of Proportionate Type LMS Adaptive Filters for Sparse System Identification VLSI 2018 Download Low Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption VLSI 2018 Download SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability VLSI 2018 Download A 3 2 GHz Supply Noise Insensitive PLL Using a Gate Voltage Boosted Source Follower Regulator and Residual Noise Cancellation VLSI 2018 Download Combating Data Leakage Trojans in Commercial and ASIC Applications With Time Division Multiplexing and Random Encoding VLSI 2018 Download A 12 bit 40 MS s SAR ADC With a Fast Binary Window DAC Switching Scheme VLSI 2018 Download A Variable Size FFT Hardware Accelerator Based on Matrix Transposition VLSI 2018 Download A 0 9 V 12 bit 100 MS s 14 6 fJ Conversion Step SAR ADC in 40 nm CMOS VLSI 2018 Download Low Power and Fast Full Adder by Exploring New XOR andX NOR Gates VLSI 2018 Download A Flexible Wildcard Pattern Matching Accelerator via Simultaneous Discrete Finite Automata VLSI 2018 Download Securing the PRESENT Block Cipher Against Combined Side Channel Analysis and Fault Attacks VLSI 2018 Download Low Complexity Methodology for Complex Square Root Computation VLSI 2018 Download ULV Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures VLSI 2018 Download Vector Processing Aware Advanced Clock Gating Techniques for Low Power Fused Multiply Add VLSI 2018 Download A High Accuracy Programmable Pulse Generator With a 10 ps Timing Resolution VLSI 2018 Download Low Phase Noise Ku Band VCO With Optimal Switched Capacitor Bank Design VLSI 2018 Download Analysis and Design of Cost Effective High Throughput LDPC Decoders VLSI 2018 Download Basic Set Trellis Min Max Decoder Architecture for Nonbinary LDPC Codes With High Order Galois Fields VLSI 2018 Download Approximate Hybrid High Radix Encoding for Energy Efficient Inexact Multipliers VLSI 2018 Download A 588 Gb s LDPC Decoder Based on Finite Alphabet Message Passing VLSI 2018 Download The Implementation of the Improved OMP for AIC Reconstruction Based on Parallel Index Selection VLSI 2018 Download Design and FPGA Implementation of a Reconfigurable Digital Down Converter for Wideband Applications VLSI 2018 Download VLSI Design of an ML Based Power Efficient Motion Estimation Controller for Intelligent Mobile Systems VLSI 2018 Download Extending 3 bit Burst Error Correction Codes With Quadruple Adjacent Error Correction VLSI 2018 Download An Energy Efficient Programmable Manycore Accelerator for Personalized Biomedical Applications VLSI 2018 Download Approximate Sum of Products Designs Based on Distributed Arithmetic VLSI 2018 Download An Efficient Fault Tolerance Design for Integer Parallel Matrix Vector Multiplications VLSI 2018 Download A Reconfigurable LDPC Decoder Optimized for 802 11n ac Applications VLSI 2018 Download A Fast and Low Complexity Operator for the Computation of the Arctangent of a Complex Number VLSI 2018 Download Design of an Area Efficient Million Bit Integer Multiplier Using Double Modulus NTT VLSI 2018 Download Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities VLSI 2018 Download Efficient FPGA Mapping of Pipeline SDF FFT Cores VLSI 2018 Download A 0 65 V 500 MHz Integrated Dynamic and Static RAM for Error Tolerant Applications VLSI 2018 Download Design of Temperature Aware Low Voltage 8T SRAM in SOI Technology for High Temperature Operation 25 C 300 C VLSI 2018 Download Approximate Error Detection With Stochastic Checkers VLSI 2018 Download A Residue to Binary Converter for the Extended Four Moduli Set 2n 1 2n 1 22n 1 22n p VLSI 2018 Download A Closed Form Expression for Minimum Operating Voltage of CMOS D Flip Flop VLSI 2018 Download A 128 Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications VLSI 2018 Download